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general description the ds2710 is ideal for in-system charging of single-cell nickel metal hydride (nimh) cells for low-current portable applications. inputs to the ds2710 include usb voltage sources and 5v regulated adapters. temperature, voltage, and charge time are monitored to provide proper fast-charging control algorithms for single-cell nimh or nickel cadmium (nicd) batteries. the ds2710 includes battery tests to detect defective or inappropriate cells such as alkaline primary batteries. applications small rechargeable devices voice recorders cordless mouse battery-powered toys features ? charges single-cell nimh cells ? switch-mode topologies supported by hysteretic control technique ? precharges deeply depleted cells ? fast-charges nimh with - v termination sensitivity of 2mv (typ) ? monitors voltage, temperature, and time for safety and secondary termination ? regulates charge current ? designed for external pmos ? rail-to-rail mosfet driver ? tiny 10-pin tdfn package (3mm x 4mm) ds2710 single-cell nimh charger ________________________________________________________________ maxim integrated products 1 ds2710 110 vp1 v ss 3 8 vn0 v dd 2 9 vn1 cs 4 7 tmr thm 5 6 ctest status tdfn (3mm top view + *ep *exposed pad. pin configuration ordering information ds2710 v dd vp1 thm cs vn0 vn1 sense charge source nimh cell ground typical operating circuit rev 0; 4/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. * ep = exposed pad. part pin-package DS2710G+ 10 tdfn-ep* DS2710G+t&r 10 tdfn-ep*
ds2710 single-cell nimh charger 2 _______________________________________________________________________________________ 2 _______________________________________________________________________________________ absolute maximum ratings recommended dc operating conditions (4.0v v dd 5.5v, t a = -20? to +70?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on all pins relative to v ss ............-0.3v to +6.0v continuous source/sink current cs ...................................20ma continuous source current status ..................................10ma operating temperature range ...........................-40? to +85? storage temperature range .............................-55? to +125? soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units supply voltage v dd (note 1) 4.0 5.5 v input voltage range ctest, tmr, thm, vp1, vn1 -0.3 v dd v dc electrical characteristics (4.0v v dd 5.5v, t a = -20? to +70?, unless otherwise noted.) parameter symbol conditions min typ max units supply current, v dd i dd operating mode (note 2) 250 1000 a uvlo threshold v uvlo v dd rising (note 1) 3.5 3.9 v uvlo hysteresis v uhys v dd falling from above v uvlo 30 mv output-voltage low, cs v ol1 v dd = 5.0v, i ol = +20ma (note 1) 1.0 v output-voltage high, cs v oh1 v dd = 5.0v, i ol = -20ma (note 1) 4.0 v output-voltage low, status v ol2 v dd = 5.0v, i ol = +2ma (notes 1, 3) 0.50 v output-voltage high, status v oh2 v dd = 5.0v, i oh = -2ma (notes 1, 3) 4.0 v threshold voltage, - v termination v - v after t tho (note 4) 1.0 2.0 3.0 mv 125 mv current-sense reference voltage v iref (notes 1, 5) -6 +6 % hysteresis, current-sense comparator v hys- comp centered ~ 0.113v 18 23 27 mv propagation time, current-sense comparator to driver output t pdly 2mv overdrive/underdrive at trip threshold (notes 4, 6) 0.1 s cs pin pullup current i cs v dd < v uvlo (note 4) 2 10 a status pin pulldown current i stat v dd < v uvlo (note 4) 2 10 a depleted cell voltage threshold v low vp1 - vn1 0.9 1.0 1.1 v overcharge voltage threshold v max- open vp1 - vn1, cs = high (note 7) 1.55 1.65 1.75 v open socket voltage threshold v max- charge vp1 - vn1, cs = low (note 7) 1.64 1.75 1.86 v offset, v max-open - v max-charge v os (note 7) 98 100 102 mv
ds2710 single-cell nimh charger _______________________________________________________________________________________ 3 note 1: voltages relative to v ss . note 2: specification does not include cs and status pin currents. note 3: status pin is active high. note 4: specification is guaranteed by design. note 5: specification applicable during charge cycle with t a = 0? to +70?. note 6: 50mv overdrive while connected to a pmos transistor (such as zxm62p02 from zetex). note 7: v bat-max1 and v bat-max1 ranges never overlap. note 8: vt hm-min , v thm-max , and v thm-stop are fixed ratios of v dd . their ranges never overlap. note 9: maximum allowable leakage on tmr to maintain suspend state. dc electrical characteristics (continued) (4.0v v dd 5.5v, t a = -20? to +70?, unless otherwise noted.) parameter symbol conditions min typ max units cold temperature detect threshold v thm-min (notes 1, 5, 8) 0.73 v dd hot temperature no-start threshold v thm-max (notes 1, 5, 8) 0.30 0.33 0.36 v dd hot temperature safety shutdown threshold v thm-stop (notes 1, 5, 8) 0.29 v dd suspend current threshold i suspend (note 9) 0.1 0.5 a presence-test current, vp1 v dd 4.0v 1.0 10 15 a reverse-leakage current, vp1 v dd = 0v, v p1 = 1.5v 2 a impedance-voltage test range v ctest 32 400 mv electrical characteristics: timing (4.0v v dd 5.5v, t a = -20? to +70?, unless otherwise noted.) parameter symbol conditions min typ max units internal time-base period t base 0.96 seconds internal time-base accuracy -10 +10 % df1 fast-charge 96.9 df2 precharge/top-off 25.0 cs output duty factor df3 maintenance 1.56 % cell test interval t ctst 31 seconds precharge timeout t pchg v cell < v low 34 minutes fast-charge termination hold-off period t tho 4 minutes fast-charge flat voltage timeout t flat v cell not increasing 16 minutes charge-timer period t ctmr r tmr = 40k 1.0 hours charge-timer accuracy r tmr = 40k -6 +6 % charge-timer range t ctmr-range 0.5 5.0 hours toggle rate, charging f charge 1 hz toggle rate, fault state f fault 4 hz
ds2710 single-cell nimh charger 4 _______________________________________________________________________________________ pin description pin name function 1 v ss device ground. connects directly to the negative terminal of the charge source. 2 cs charge source. feedback control for switching circuitry. 3 v dd power-supply input. connects to the positive terminal of the charge source through a decoupling network. 4 thm thermistor input. connects to a thermistor located near the cell and a resistor-divider from the v dd pin. 5 status status output. drives an external led or microprocessor input to indicate charge status. 6 ctest impedance test. connects to v ss through an external resistor to set the impedance-test threshold. 7 tmr fast-charge timer. connects to v ss through an external resistor to set the fast-charge timeout period. 8 vn0 current-sense negative input. connects to the charge source side of the external sense resistor. 9 vn1 current-sense positive input. connects to the cell side of the external sense resistor. 10 vp1 cell voltage sense. the voltage of the cell is monitored through this input pin. ep exposed pad. connects to v ss . ds2710 bias oscillator watchdog abort vp1 i ptst uvlo 3.5v v dd status ctest status maintenance charge top-off charge suspend precharge presense test state machine fast-charge and cell tests voltage and temperature measurement duty- factor control vn1 thm cs 0.125v 0.1 a v ss vn0 cell test tmr charge timer figure 1. block diagram
detailed description charge algorithm overview the ds2710 controls switch-mode topology charging of a single nimh cell from a voltage-regulated charge source. the ic is reset in one of two ways: with the application of power to the ds2710 or after exiting suspend state. once one of these conditions occurs, the ds2710 enters the presence state and waits for a cell to be inserted before starting a charge cycle. once a cell is detected, the ds2710 enters precharge state and begins qualification to prevent fast charging of deeply depleted cells or charging under extreme temperature conditions. precharging is performed at a reduced rate until the cell reaches 1v. the algorithm then proceeds to the fast-charge state, which includes cell tests to avoid accidental charging of alka- line cells or nimh cells that are worn out or damaged. fast charging continues as long as all the cell qualifica- tion criteria are met. fast charging terminates by the - v (negative delta voltage) method. the top-off charge phase follows to completely charge the cell. after the top-off charge timer expires, the ds2710 enters the maintenance state to indefinitely keep the cell at a full state of charge. maximum voltage, temper- ature, and charge-time monitoring during all charge phases act as secondary or safety termination methods to provide additional protection from overcharge. any error condition occurring during charge forces the ds2710 into the fault state and charging terminates. charging can be halted at any time by floating the tmr pin, which forces the ds2710 into suspend state. once a charge is complete either normally or by fault, the ds2710 remains in the final state (mainte- nance or fault) until the cell is removed, the ic is power cycled, or the ic is forced into suspend state. afterwards, the ds2710 returns to presence state and the charge cycle begins again. an internal oscillator provides the main clock source used to generate timing signals for chip operation. the precharge timer, hold-off timers, and timing for cs operation and cell testing are derived from this time base. if the internal clock should ever fail, a watchdog- detection circuit halts charging. the watchdog-safety circuit and charge timer set by the tmr pin are derived from oscillators other than the main clock source. figure 1 is the ds2710 block diagram and figure 2 is the state diagram. power-on reset (por) the uvlo circuit serves as a power-up and brownout detector by monitoring v dd to prevent charging until v dd rises above v uvlo , or when v dd drops below v uvlo - v uhys . if undervoltage lockout is active, charging is prevented, the state machine is forced to the por state, and all charge timers are reset. presence the ds2710 enters the presence state whenever the tmr pin is not floating and v dd > v uvlo , indicating that the charge source is present. the ds2710 remains in the presence state until a cell is inserted into the circuit, causing the voltage of vp1 - vn1 to fall below 1.65v (v max-open ) and the cell temperature is inside a valid charging range between 0? and +45? (t thm-min and t thm-max when used with recommend- ed thermistor and resistor values). if both these condi- tions are met, the ds2710 enters precharge. if a cell is inserted but the temperature is outside the valid charging range, the ds2710 remains in the presence state until the cell temperature falls within the valid charging range. precharge the ds2710 enters the precharge state when a valid cell voltage is detected and the cell temperature as measured by the ds2710 thermistor circuit is within the valid charging range. the ds2710 precharges the cell by regulating the voltage drop across the sense resis- tor to 113mv with a 25% duty cycle. the status out- put toggles at 1hz to indicate the cell is being precharged. precharging lasts until the measured cell voltage exceeds 1.0v (v low ), at which time the ds2710 enters the fast-charge state. if the cell volt- age does not exceed v low within 30min (t pchg ) or if the cell temperature exceeds +50? (t thm-stop ) at any time during precharge, the ds2710 enters the fault state. if at any time during precharge the cell voltage exceeds 1.75v (v max-charge ), the ds2710 determines that the cell has been removed and enters the fault state. fast-charge in the fast-charge state, the ds2710 regulates the average voltage across the sense resistor to 113mv. the status output is held high to indicate the cell pack is being charged. during fast-charge, the ds2710 performs a cell test every 31s. the cell test state is responsible for determining when charge is complete. as secondary overcharge protection, the ds2710 terminates fast-charge and enters top- off based on a time delay set by the external resistor on the tmr pin. this resistor value can set the sec- ondary charge termination delay to anywhere from 30min up to 5hr. if the cell temperature exceeds +50? at any time during fast-charge, the ds2710 enters ds2710 single-cell nimh charger _______________________________________________________________________________________ 5
ds2710 single-cell nimh charger 6 _______________________________________________________________________________________ precharge cs = active 25% df status = 1hz toggle cell test cs = inactive status = high fast-charge cs = active status = high top-off cs = active 25% df status = high maintenance cs = active 1.56% df status = low fault cs = inactive status = 4hz toggle presence cs = inactive status = low t < fast timeout t < top-off timeout t > fast timeout t > +50 c pass 31s interval suspend cs = inactive status = low r tmr > r suspend (asynchronously from anywhere) r tmr < r suspend v dd > v uvlo (3.5v) v dd < v uvlo - v uhys (asynchronously from anywhere) t < t pchg and v cell < 1.0v v cell > 1.0v and t < t pchg and t < +50 c t > t pchg or t > +50 c or v cell > v max * t > +50 c or t > top-off timeout - v detect or flat voltage detect *v max represents v max-charge when the cs output is active and v max-open when the cs output is inactive. v cell > 1.75v or t < 0 c or t > +45 c v cell > 1.75v v cell < v max-open fail: v cell > v max-open or v > ctest v cell > v max * v cell > v max * por cs = inactive figure 2. state diagram
the maintenance state. if at any time during fast- charge the cell voltage exceeds v max-charge , the ds2710 determines that the cell is either overcharged or has been removed, and enters the fault state. cell test cell test is performed once every 31s during fast- charge to determine if charging is complete. during cell test, the cs output is held high to prevent charging. the cell? voltage is measured and com- pared against prior readings. the maximum cell volt- age measurement during the charge is retained. if a cell? voltage falls more than 2mv (v - v ) from its peak reading, the fast-charge terminates successfully and moves to top-off. the ds2710 also moves to top-off if the cell? voltage reading does not exceed the maximum over a 16min period (t flat ). a hold-off period for - v and flat voltage detection begins at the start of fast charging and prevents false termination in the first 4min of the charge cycle (t tho ). the impedance of the cell is also measured during cell test. the cell? open-circuit voltage is compared against the voltage of the cell under charge. the differ- ence is compared against the impedance threshold set by the ctest pin. if the difference exceeds the thresh- old set by ctest, the cell? impedance is considered to be too high for charging and the ds2710 enters the fault state. the ds2710 also enters fault state if any voltage reading in cell test exceeds the v max-open threshold. top-off in the top-off state, the ds2710 charges at 25% the rate of fast-charge. the voltage across the sense resistor is regulated to 113mv with a 25% duty cycle. the status output is held high to indicate the cell pack is being charged. the charge timer is reset and restarted with a timeout period of one-half the fast-charge duration. when the charge timer expires or if the measured temperature exceeds +50?, the charger enters the maintenance state. if the cell voltage is greater than v max-charge during the 25% of time when charge current is applied or v max-open during the remaining time, top-off is exit- ed early and the ds2710 goes to fault. maintenance the ds2710 enters the maintenance state whenever the charge completes normally or if the measured cell temperature exceeds +50? during the charge. the status pin is driven low to indicate top-off has completed. the cell? state of charge is maintained indefinitely by continuing a 1.56% duty-cycle charge of the cell. the ds2710 remains in the maintenance state until the cell is removed, the ds2710 is power cycled, or the ds2710 is forced into suspend state. fault the ds2710 can enter fault from any charge state if the cell voltage exceeds v max-charge any time when charge current is applied (cs low) or v max-open at any time when no charge current is flowing (cs high). in addition, fault can be entered during precharge if the cell? temperature exceeds +50? or the precharge timer expires, or during fast-charge if impedance threshold is exceeded. in the fault state, cs is forced high to prevent charging and the status output toggles at a 4hz rate to indicate that an error has occurred. the ds2710 remains in fault until a cell voltage greater than 1.75v (v max-charge ) is detected, indicating that the cell has been removed. the ds2710 then enters the presence state and waits for the next cell insertion. suspend suspension of charge activity is possible by floating the tmr pin (r tmr > r suspend ). the cs output is pulled to v dd to disable the charge control fet to prevent cur- rent flow to the cell. when the tmr connection is restored, charging begins from the presence state with all timers reset. the suspend state is useful as a means to stop charging by the application circuit, such as with a microcontroller signal. ds2710 single-cell nimh charger _______________________________________________________________________________________ 7
ds2710 charge-current regulation the ds2710 regulates charge current by maintaining a constant average voltage across an external sense resistor connected between the vn1 and vn0 pins. vn1 and vn0 drive an internal comparator in the ds2710 to switch the cs output on and off to drive a regulating pnp bipolar or a pmos transistor. hysteresis on the comparator input provides noise rejection. the ds2710 regulates the charge current during fast- charge to maintain a voltage drop across the sense resistor as follows: v sense = v iref - 0.5 x v hys-comp = 0.113v (typ) figure 3 shows the sense resistor voltage and cs pin voltage of the regulating circuit during normal operation. charging with load applied nimh cells have a low, but finite, impedance. if load current is flowing out of the battery, an internal voltage drop appears at the battery terminals. this can interfere with the ctest and - v detection. if the load current is variable, early termination is more likely than if the load current is constant. if the load? ground is connected to the negative terminal of the cell (vn0), load current flows through the current-sense resistor, resulting in less charge current to the battery. the load-current return path should be to charger ground to reduce the likeli- hood of false termination or impedance-test errors. charging with load applied is not recommended. temperature monitoring accurate temperature sensing is needed to detect tem- perature fault conditions. connecting an external 10k ntc thermistor between thm and v ss and a 10k bias resistor between v dd and thm allows the ds2710 to sense temperature. to accurately monitor the cell, the thermistor should make physical contact either to the cell or cell tabs. table 1 shows several rec- ommended 10k thermistors. min, max temperature compare the voltage thresholds of the thm input (v thm-min , v thm-max ) are set to allow charging to start if the ther- mistor temperature is between 0 c and +45 c when using the recommended 10k bias resistor and 10k thermistor circuit. if precharging is in progress and the voltage on thm reaches v thm-stop , precharging stops and a fault condition is generated. if the volt- age on thm reaches v thm-stop during fast- charge or top-off, charging stops and the ds2710 enters the maintenance state. fast-charge and single-cell nimh charger 8 _______________________________________________________________________________________ time v cs v oh1 v ol1 v iref v sense (dc) v iref - v hys-comp v sense not drawn to scale figure 3. ideal comparator input and charge control output waveforms 0.75 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0 1020304050 divider output temperature ( c) voltage ratio figure 4. ratio of thm pin to v dd pin over temperature temperature ( c) thm threshold ratio of v cbias thermistor resistance (k ) semitec 103at-2 fenwal 197-103lag-a01, 173-103laf-301 min 0.73 27.04 0 +4 max 0.33 4.925 +45 +42 stop 0.29 4.085 +50 +47 table 1. thm thresholds
top-off complete normally if the cell temperature remains below this threshold. used with a 10k resistor, the semitec 103at-2 pro- vides approximately 0.9% full scale-per-degree sensi- tivity. figure 4 shows this linearity curve. the left axis is the ratio of the sensed voltage to the divider? input voltage (v dd ). charge-status output the ds2710 indicates the state of charge and the charge results on the status output pin. when no cell is present, the output is driven to a logic-low. any led attached to the status pin is off. when a cell is insert- ed, status oscillates in a 1hz, 50% duty-cycle pattern to indicate the cell is precharging. once the ds2710 transitions to fast-charge, the status output goes to logic-high and stays high until the end of top-off. status returns to logic-low for maintenance charge and remains at logic-low until the cell is removed or the ds2710 is power cycled. if a fault occurs during charging, status toggles at a fast 4hz, 50% duty- cycle rate until the cell is removed. table 2 summarizes the status output and led operation for each charge condition. charge-rate selection the charge rate is determined by an external sense resistor connected between the vn1 and vn0 pins. the ds2710 regulates the charge current to maintain a volt- age drop of v iref - 0.5 x v hys-comp across the sense resistor during fast-charge: v sense = v iref - 0.5 x v hys-comp = 0.113v (typ) the sense resistor can therefore be selected by: r sense = 0.113v/desired fast-charge current the effective fast-charge rate is equal to 0.969 times the regulated current limit, top-off rate is 0.25 times the regulated current, and maintenance charge rate is 0.0156 times the regulated current. table 3 shows the charge rates for charging three different cell capac- ities using a 565ma (0.200 sense) current source and a 1130ma (0.100 sense) current source. ds2710 single-cell nimh charger _______________________________________________________________________________________ 9 table 2. led display patterns based on charge state charge state no battery precharge fast-charge/ top-off maintenance fault status pin logic-low oscillates at 1hz, 50% duty cycle logic-high logic-low oscillates at 4hz, 50% duty cycle status pin led off 1hz toggle on off 4hz toggle table 3. charge-rate examples 565ma charge rate (0.200 ) at cell capacity 1130ma charge rate (0.100 ) at cell capacity state 900mah 1700mah 2200mah 900mah 1700mah 2200mah fast-charge c/1.64 c/3.10 c/4.00 c/0.82 c/1.55 c/2.0 precharge/top-off c/6.37 c/12.0 c/15.5 c/3.19 c/6.0 c/7.75 maintenance c/102 c/193 c/249 c/51 c/96 c/125
ds2710 timeout selection fast-charge state normally operates until - v termi- nation. in the event that termination does not occur cor- rectly, a safety timeout is required. this timeout is set by an external resistor on the tmr pin to v ss and pro- vides secondary protection against significant over- charging. the value of the tmr resistor should be chosen so that the timeout is greater than the fast- charge time expected in the application, but not so much greater that its protection is compromised. if the timer expires during fast-charge, the timer count is reset and charging proceeds to the top-off charge state. the tmr resistor also sets the timed charge duration of top-off state. the top-off timeout peri- od is fixed at half the fast-charge timeout period. when the timer expires in top-off, the ds2710 enters the maintenance state. resistors can be selected to support fast-charge timeout periods of 0.5hr to 5hr and top-off timeout periods of 0.25hr to 2.5hr. the programmed fast- charge time approximately follows the equation: t(minutes) = 1.5 x r tmr ( )/1000 impedance-test threshold selection the ds2710 tests the cell impedance every 31s while in fast-charge state. impedance is measured by comparing the cell voltage during normal charging to the cell voltage with no charge current (cs output held high). the resulting voltage difference is compared against the threshold set by an external resistor from ctest to v ss . the detection threshold can be set from 32mv to 400mv. the following formula approximates the setting for the detection threshold: v test = 8000/r ctest (value in volts) since the charge rate is controlled by the external sense resistor (r sense ) between vn1 and vn0, the test threshold can be expressed as impedance as follows: impedance threshold = ( 8000/r ctest )/( 0.113/r sense ) = 70796 x ( r sense /r ctest ) for example, an application charging at 1.13a (r sense = 0.100 ) would use a 47k resistor on the ctest pin to set the impedance threshold to 0.150 . application circuit figure 5 shows a typical ds2710 application circuit for charging a nimh cell from a usb port or other 5v charge source capable of supplying 0.5a. q1, l1, c2, and d2 form a switching buck-regulator circuit con- trolled by the cs pin of the ds2710. current is regulat- ed through the current-sense resistor, r9, by switching q1 on and off as the sense resistor voltage ramps up and down toward the preset sense voltage thresholds. the 0.100 sense resistor along with the dc ground- referenced sense threshold level of v iref - 1/2 v hys- comp sets the average charge current in the example to 1.13a. the sense resistor should have a proper power rating for the chosen charge current. the tmr resistor is set to 100k for a timeout of 2.5hr. this is appropriate for cells with a capacity of approxi- mately 2200mah when charged with the 1.13a charge current. the ctest resistor is set to 47k for an imped- ance-test threshold of approximately 0.150 when charging at 1.13a. additionally, r6 protects the vp1 pin from any stress applied to the exposed tabs of a loose nimh cell; r3 creates a weak pullup to offset the leak- age through d2, which might otherwise cause a false cell detection; and r1/c1 creates a bypass filter on the v dd pin of the ic. the value of l1 in figure 5 represents a moderate switching speed of ~ 200khz for fast-charge state. l1 can be adjusted to fit specific application goals as long as the associated change in switching speed does not exceed the circuit? ability to maintain proper regulation of the sense-resistor voltage. all capacitors should be ceramic surface-mount types of good quality where possible. the 10? capacitor can be of any type that meets the application requirements. all resistors not previously mentioned are standard surface-mount types. application pcb layout proper layout rules must be followed to ensure a suc- cessful application circuit. for all modes of operation, currents in excess of 1a can flow through the charge and discharge paths (usb charging is specification lim- ited to 500ma). all these paths should be properly sized to handle the worst-case current flow, whether from charging or from powering the load with the battery. switch-mode operation presents challenges with fast voltage and current transients. proper switch-mode buck power-supply layout should always be observed. single-cell nimh charger 10 ______________________________________________________________________________________
ds2710 single-cell nimh charger ______________________________________________________________________________________ 11 ds2710 v dd thm status vp1 vn1 vn0 tmr ctest v ss cs r6 1k r3 270k r2 1k r1 150 r4 10k r7 100k r8 47k r9 0.1 1w 1s nimh cell c1 1 f c3 10 f ceramic q1 zxm62p02e6 +5v (usb+) ground (usb-) l1 15 h siscdrh74m-150r d2 1w b340a-13 schottky c2 10 f ceramic d1 green sma rt1 103at-2 figure 5. typical application circuit for usb port charging referring to the example circuit and layout of figure 6, the loop labeled as loop1 encompassing c in , q switch , and d switch should be kept as small as possible to minimize the change in loop area that occurs when switching from the off to the on state and vice versa. loop2 should also be minimized as much as practical, although it contains dc current components for the most part. the returning ground currents should be allowed to follow a path on a layer directly under the outgoing path since the high-fre- quency components try to follow the path of least impedance. low esr and esl capacitors should be used when possible and for all capacitors 10? and smaller. typical surface-mount ceramic types with an x5r or better dielectric are recommended. another important layout detail is the connection of the sense resistor. proper kelvin connection layout should be used to ensure the signal quality viewed by the sensing circuit inside the ds2710 is adequate. figure 7 shows a recommended connection of the sense lines to the resistor footprint. package type package code document no. 10 tdfn-ep t1034+1 21-0268 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages .
ds2710 single-cell nimh charger maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. c i d s l s q s control control charge source side charge source side battery side backside ground plane battery side loop areas minimized loop1 loop2 c o r g c in c out r gate q switch d switch l switch figure 6. switching circuit with example layout r sns sense+ sense- battery- battery- sense+ sense- r sns charge source- charge source- proper kelvin connection at sense resistor sense traces run close together to minimize loop inductance figure 7. sense resistor connection layout

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